This application is based on Japanese Patent Applications HEI 11-309850 filed on Oct. 29, 1999, HEI 11-245324 filed on Aug. 31, 1999, and 2000-213685 filed on Jul. 14, 2000, the entire contents of which are incorporated herein by reference.
a) Field of the Invention
The present invention relates to a thin film transistor, a liquid crystal display substrate, a MIS type field effect transistor (MISFET), and their manufacture methods, and more particularly to a transistor having a lightly doped drain structure, a liquid display substrate having such transistors, and their manufacture methods.
b) Description of the Related Art
Thin film transistors (TFT) are used as switching elements of pixels of an active matrix type liquid crystal display device. A small off-current of TFT is necessary for holding electric charges accumulated by a pixel electrode. The off-current can be reduced by adopting a lightly doped drain (LDD) structure.
If both the source and drain regions of TFT have the LDD structure, an on-current reduces. In order to reduce the off-current and retain a sufficient on-current, it can be considered preferable if the LDD structure is formed only on the drain side.
For example, in order to form the LDD structure in only the drain region, first impurity ions are implanted into the drain and source regions at a low concentration. Thereafter, the area in the drain region at the low concentration is covered with a resist mask and impurity ions are implanted at a relatively high concentration. The source region is not covered with the resist mask. If the gate length is short, a high precision of position alignment is required when a resist mask is formed to cover the low concentration region on the drain side and expose the source region.
A TFT using a polysilicon thin film has a carrier mobility higher than a TFT using amorphous silicon. Therefore, by using polysilicon TFT, an image display area and its driver circuit can be formed on the same substrate. A larger on-current is required for TFT in the peripheral circuit than a switching TFT of each pixel. In this context, it may occur that the LDD structure is adopted for TFT in the pixel area and not for TFT in the peripheral circuit.
If the LDD structure is adopted for the source and drain regions of TFT in the pixel area and not adopted for TFT in the peripheral circuit, the number of photolithography processes increases more than if the LDD structure is adopted for all TFTs. An increase in the number of photography processes results in a higher manufacture cost and a lower manufacture yield.
It is an object of the present invention to provide TFT having a small off-current and not requiring a high alignment precision even if the gate length is short.
It is another object of the present invention to provide a liquid crystal display substrate in which TFT in an image display area has a small off-current and TFT in a peripheral circuit has a large on-current, and a method of manufacturing such a substrate.
It is another object of the present invention to provide a method of manufacturing TFT or MISFET having the LDD structure, capable of suppressing an increase in the number of manufacture processes as small as possible.
According to one aspect of the present invention, there is provided a thin film transistor comprising: a current path pattern defining a current path, the current path pattern being made of semiconductor material and formed on an insulating principal surface of a substrate; a gate pattern three-dimensionally crossing the current path pattern at least in first and second cross areas, the gate pattern defining a channel region of the current path pattern in an area superposed upon by the gate pattern; and a gate insulating film disposed between the current path pattern and the gate pattern in the first and second cross areas, wherein the current path pattern has an LDD structure on both sides of the channel region in the first cross area, the LDD structure including low concentration regions in contact with the channel region and high concentration regions in contact with the low concentration regions, and has an impurity concentration in areas in contact with the channel region in the second cross area higher than an impurity concentration of the low impurity concentration regions.
Since the LDD structure is formed on both sides of the channel region in the first contact area, it is not necessary to mask only one side of the gate during manufacture. Accordingly, a high position alignment precision is not required even if the gate length is short. Since the LDD structure is formed in one of the first and second cross areas, an off-current can be made small.
According to another aspect of the present invention, there is provided a liquid crystal display substrate comprising: a plurality of gate bus lines extending in a row direction and formed on an insulating principal surface of a substrate; a plurality of drain bus lines extending in a column direction and formed on the principal surface of the substrate, the drain bus line being electrically insulated from the gate bus line in a cross area in which the gate bus line and the drain bus line cross each other; a pixel electrode disposed in each of cross areas between the gate bus line and the drain bus line; a current path pattern disposed in and along each cross area between the gate bus line and the drain bus line, the current path pattern being made of semiconductor material and three-dimensionally crossing a corresponding one of the gate bus lines at least in two cross areas, a channel region of the current path pattern being formed in an area superposed upon by the gate bus line, a first end portion of the current path pattern being electrically connected to a corresponding one of the drain bus lines, and a second end portion of the current path pattern being electrically connected to a corresponding one of the pixel electrodes; and a gate insulating film disposed between the gate bus line and the current path pattern in the cross area, wherein the current path pattern has an LDD structure on both sides of the channel region nearer to the first end portion, the LDD structure including low concentration regions in contact with the channel region and high concentration regions in contact with the low concentration regions, and has an impurity concentration in areas in contact with the channel region nearer to the second end portion higher than an impurity concentration of the low impurity concentration regions.
Since the LDD structure is formed on both sides of the channel region nearer to the first end portion, it is not necessary to mask only one side of the gate during manufacture. Accordingly, a high position alignment precision is not required even if the gate length is short. Since the LDD structure is formed in one of the first and second cross areas, an off-current can be made small.
If the substrate is rotated by 90xc2x0, the row direction and the column direction are replaced with each other. Namely, in the present specification, the row direction and the column direction mean the two directions intersecting with each other and do not necessarily mean horizontal and vertical directions.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor display substrate, comprising the steps of: preparing a substrate having an insulating principal surface, and an image display area and a peripheral circuit area defined in a plane of the principal surface, the peripheral circuit area being disposed at a side of the image display area; forming a plurality of first current path patterns distributed in a matrix shape on the principal surface of the substrate in the image display area and a second current path pattern in the peripheral circuit area, in such a manner that each of the first current path patterns includes a portion flowing current at least in a column direction and the second current path patter includes a portion flowing current at least in a row direction; covering the first and second current path patterns with a gate insulating film; forming a plurality of gate patterns on the gate insulating film in such a manner that the gate pattern crosses the column directionally flowing current portion of the first current path pattern in the image display area and crosses the row directionally flowing current portion of the second current path pattern in the peripheral circuit area; implanting impurity ions into the first and second current path patterns by using the gate patterns as a mask; and irradiating an energy beam into the first and second current path patterns along an oblique direction relative to a plane of the principal surface to activate doped impurities so that the energy beam is irradiated in the first current path pattern in a shaded state of one of both sides of the gate pattern and irradiated in the second current pattern on both sides of the gate pattern.
The energy beam is not irradiated in a region of the shaded state of one of both sides of the gate bus line, and impurities are not activated. The region whose impurities are not activated serves as the low concentration region of the LDD structure. If two TFTs are formed having gates whose extension directions are shifted by 90xc2x0, one TFT can have a one-side LDD structure, and the other TFT can have a both-side LDD structure.